1. Field of the Invention
The invention relates to a memory, more particularly to a memory with a current leakage suppressor.
2. Description of the Related Art
FIG. 1 illustrates the structure of a conventional memory. Each memory cell 102 includes a storage element 104 and a transistor 106 that are coupled in series. The storage element may be a phase change storage element. Each bit line BL relates to a bit line selector 108. The current generator 110 is operable to generate a control current I that is sent into the storage elements according to the states of the bit line selectors and the transistors, wherein the states of the transistors are controlled by word line control signals WL0˜WLN. In a case wherein the storage element 104 is a phase change element, the state of the storage element 104 is dependent on the current flowing therethrough, and may be switched between a read state, a crystalline state and an amorphous state. The crystalline state and the amorphous state relate to low impedance and high impedance, respectively, and are used to represent digital value ‘0’ and ‘1’.
In an ideal case, the control current I should be zero when the memory is not being accessed. However, a small control current I still flows out from the current generator 110 because of current leakage, and the transistors, such as the transistor 106, of the memory cells are not completely turned off because of the current leakage thereof. Thus, although the memory may not be accessed, power consumption of the memory may be wasted, and inexorably high.